发明名称 |
A 2-D GATHER INSTRUCTION AND A 2-D CACHE |
摘要 |
A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image. |
申请公布号 |
US2013054899(A1) |
申请公布日期 |
2013.02.28 |
申请号 |
US201113220402 |
申请日期 |
2011.08.29 |
申请人 |
GINZBURG BORIS;MARGULIS OLEG |
发明人 |
GINZBURG BORIS;MARGULIS OLEG |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|