发明名称 DETERIORATION DIAGNOSTIC CIRCUIT AND DETERIORATION DIAGNOSTIC METHOD
摘要 <p>In order to more accurately measure a deterioration state of a semiconductor integrated circuit by means of a simpler configuration, a deterioration diagnostic circuit of the present invention is provided with: a block to be tested, which includes a first circuit to be subjected to deterioration diagnosis; a reference block, which includes a second circuit that is provided with a configuration identical to that of the first circuit; a determining means, which determines whether elements constituting the block to be tested are deteriorated or not by comparing characteristics of first signals, which are outputted from the block to be tested in the cases where signals indicating measurement mode are inputted, with characteristics of second signals outputted from the reference block; and a control means, which outputs, to the determining means, the signals that indicate the measurement mode.</p>
申请公布号 WO2013027739(A1) 申请公布日期 2013.02.28
申请号 WO2012JP71109 申请日期 2012.08.15
申请人 NEC CORPORATION;SANEYOSHI, EISUKE 发明人 SANEYOSHI, EISUKE
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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