SYSTEME DE SYNCHRONISATION DE TRAME

摘要

A binary information signal having a given bit rate and either one of two different synchronization codes and two local binary synchronization reference signals are applied to a digital comparison circuit, the two output signals indicating a match or mismatch between the successive adjacent bits of the information signal and the associated one of the reference signals. The two output signals are OR-ed and AND-ed with these functions being applied to a common decision circuit having a decision level resulting in a "1" output when the decision level is not exceeded and a "0" output when the decision level is exceeded. Search logic operates on the above AND function, or a separately produced AND function, of the two output signals and cooperates with the output of the decision circuit to achieve synchronization to either of the two synchronization code patterns. The search logic is described as employing the immediate response circuit and technique, the look-ahead technique employing one shift register and the look-ahead technique employing two shift registers.