发明名称 MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD
摘要 A memory unit stores the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations. An OS (121) updates the number of time intervals; specifies a time stretch during which the number of time intervals stays abode a threshold; and sets, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power. When an operation is newly detected, the OS (121) sets a first power supply mode in which at least two cores are supplied with power, and switches, when the time interval goes beyond the time stretch, the first power supply mode to a second power supply mode in which less cores are supplied with power than in first power supply mode.
申请公布号 EP2562617(A1) 申请公布日期 2013.02.27
申请号 EP20100850237 申请日期 2010.04.22
申请人 FUJITSU LIMITED 发明人 SUZUKI, TAKAHISA;YAMASHITA, KOICHIRO;YAMAUCHI, HIROMASA;KURIHARA, KOJI
分类号 G06F1/26;G06F1/32 主分类号 G06F1/26
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