发明名称
摘要 <P>PROBLEM TO BE SOLVED: To provide a display control technique for controlling the timing of input of a data signal to a display device in a smaller space on a substrate using a more inexpensive component. <P>SOLUTION: A CPU 102 outputs a power supply signal to a display 103 through a power supply signal line 106, and also outputs the data signal to a data signal control circuit 104 through a data signal line 107 with a predetermined time lag. The data signal control circuit 104 temporarily holds the data signal once inputting it from a graphic processor 101, and outputs the data signal through a data signal line 108 in response to input of the power supply signal as a control signal from a capacitor 105 on a power supply signal line 109 branching off from the power supply signal line 106. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP5155077(B2) 申请公布日期 2013.02.27
申请号 JP20080238506 申请日期 2008.09.17
申请人 发明人
分类号 G09G5/00;G09G3/20;G09G5/18 主分类号 G09G5/00
代理机构 代理人
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