| 摘要 |
An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.
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