| 摘要 |
An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal. |
