发明名称 Integrated high-K/metal gate in CMOS process flow
摘要 A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
申请公布号 US8383502(B2) 申请公布日期 2013.02.26
申请号 US201113186572 申请日期 2011.07.20
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;CHEN RYAN CHIA-JEN;LIN YIH-ANN;LIN JR JUNG;MOR YI-SHIEN;CHEN CHIEN-HAO;HUANG KUO-TAI;CHEN YI-HSING 发明人 CHEN RYAN CHIA-JEN;LIN YIH-ANN;LIN JR JUNG;MOR YI-SHIEN;CHEN CHIEN-HAO;HUANG KUO-TAI;CHEN YI-HSING
分类号 H01L21/3205;H01L21/4763 主分类号 H01L21/3205
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