发明名称 Process for the preparation of silicon wafer with reduced slip and warpage
摘要 Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 μm from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ≧1×1012/cm3, and the density of BSFs is ≦̸1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ≧200 nm of not more than 1×107/cm3.
申请公布号 US8382894(B2) 申请公布日期 2013.02.26
申请号 US20090605926 申请日期 2009.10.26
申请人 SILTRONIC AG;NAKAI KATSUHIKO;FUKUDA MASAYUKI 发明人 NAKAI KATSUHIKO;FUKUDA MASAYUKI
分类号 C30B15/14 主分类号 C30B15/14
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