发明名称 Phase-lock in all-digital phase-locked loops
摘要 This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.
申请公布号 US8384488(B2) 申请公布日期 2013.02.26
申请号 US20090575196 申请日期 2009.10.07
申请人 INTEL MOBILE COMMUNICATIONS GMBH;MENDEL STEFAN 发明人 MENDEL STEFAN
分类号 H03B5/12 主分类号 H03B5/12
代理机构 代理人
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