| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem with a conventional scan test method, in which a semiconductor device having a high operation clock frequency cannot be tested with power supply voltage fluctuations suppressed. <P>SOLUTION: The scan test method of the present invention includes the steps of: inputting a clock signal SCLK to scan flip-flops 21-2n to set a first test pattern to the scan flip-flops 21-2n; inputting a clock signal RCLK having a higher frequency than the clock signal SCLK to the scan flip-flops 21-2n and performing control so as to set the scan flip-flops 21-2n to a hold mode in which retained values are held regardless of the clock signal RCLK, and releasing the hold mode and performing control so as to set the scan flop-flops 21-2n to a test result acquisition mode in which the retained values are updated according to the output of a test target circuit; and updating the values, which are retained by the scan flip-flops 21-2n, by using two pulses of the clock signal RCLK in the test result acquisition mode. <P>COPYRIGHT: (C)2013,JPO&INPIT |
