发明名称 CLOCK GENERATION DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generation device that generates a clock synchronous with a plurality of different reference frequencies and reduces noise generation and power consumption during a free running operation. <P>SOLUTION: A plurality of external reference clocks can be input into the clock generation device. Signal level detection circuits 24, 25 detect band-specific levels of an input external reference signal. In response to the detected signal levels, a microcontroller 4 enables a clock selection circuit 34 to output an external reference clock via a free running control signal and selects an external reference clock at an appropriate level via a selection control signal if only one external reference signal is at an appropriate level, and if not, disables the clock selection circuit 34 from outputting an external reference clock via the free running control signal, and powers down a PLL-IC 5 and causes a voltage-controlled oscillator 9 to effect free running oscillation on the basis of a voltage from a free running control DC voltage generation circuit 6. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013038548(A) 申请公布日期 2013.02.21
申请号 JP20110172167 申请日期 2011.08.05
申请人 NIPPON DEMPA KOGYO CO LTD 发明人 SHIOBARA TAKESHI;ONISHI NAOKI;INAI NAOTO
分类号 H03L7/183;H03L7/14 主分类号 H03L7/183
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