发明名称 WATCHDOG TIMER CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To detect a failure of an output operation of an error signal in a watchdog timer circuit. <P>SOLUTION: The watchdog timer circuit includes: a selection signal output circuit for outputting a selection signal which toggles in accordance with an initialization signal; first and second counters to be initialized in accordance with the initialization signal for outputting first and second overflow signals when they are overflowed; a first selector for selecting either the second overflow signal or a predetermined clock signal in accordance with the selection signal, and for outputting the signal to the first counter as a clock signal for count; a second selector for selecting either the first overflow signal or the predetermined clock signal in accordance with the selection signal, and for outputting the signal to the second counter as the clock signal for count; and a third selector for selecting either the first overflow signal or the second overflow signal in accordance with the selection signal, and for outputting the signal. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013037635(A) 申请公布日期 2013.02.21
申请号 JP20110175297 申请日期 2011.08.10
申请人 RENESAS ELECTRONICS CORP 发明人 KATO NORIO
分类号 G06F11/30 主分类号 G06F11/30
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