发明名称 |
INTERLAYER DIELECTRIC STRUCTURE AND METHOD MAKING THE SAME |
摘要 |
The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process. |
申请公布号 |
US2013043539(A1) |
申请公布日期 |
2013.02.21 |
申请号 |
US201113212904 |
申请日期 |
2011.08.18 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;CHANG JEN-CHI;LIN CHUN-LI;HSU KAI-SHIUNG;KUO MING-SHIOU;LEE WEN-LONG;LEU PO-HSIUNG;LIU DING-I |
发明人 |
CHANG JEN-CHI;LIN CHUN-LI;HSU KAI-SHIUNG;KUO MING-SHIOU;LEE WEN-LONG;LEU PO-HSIUNG;LIU DING-I |
分类号 |
H01L27/092;H01L21/336;H01L21/8238 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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