发明名称 SCAN PATTERN CREATING TECHNIQUE, PROGRAM, SCAN PATTERN CREATING DEVICE, TESTER AND TEST METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a test pattern creating method to reduce the time required for a scan test. <P>SOLUTION: A test pattern creating method comprises the steps of: reading information regarding a combinational logic circuit and at least one scan chain from a recording medium and extracting sequentially from flip-flops closer to the input side of the at least one scan chain (Step S21); determining necessity of an expected value to collate with capture data taken from the combinational logic circuit through scan capture operations by the extracted flip-flops (Steps S22-S25); acquiring the number of flip-flops existing successively from the input side where the expected value is determined not to be necessary (Step S27); and determining a difference between the total number of flip-flops included in the scan chain and the number of acquired flip-flops as the number of scan shifts after the scan capture operations (Step S28). <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013036874(A) 申请公布日期 2013.02.21
申请号 JP20110173708 申请日期 2011.08.09
申请人 RENESAS ELECTRONICS CORP 发明人 SAKANO NORIYUKI
分类号 G01R31/28;G06F11/22;G06F17/50;H01L21/822;H01L27/04 主分类号 G01R31/28
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