发明名称 |
SYSTEM CACHING USING HETEROGENOUS MEMORIES |
摘要 |
A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.
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申请公布号 |
US2013046934(A1) |
申请公布日期 |
2013.02.21 |
申请号 |
US201113209439 |
申请日期 |
2011.08.15 |
申请人 |
NYCHKA ROBERT;JOHNSON WILLIAM MICHAEL;KRUEGER STEVEN D. |
发明人 |
NYCHKA ROBERT;JOHNSON WILLIAM MICHAEL;KRUEGER STEVEN D. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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