| 摘要 |
FIELD: information technology.SUBSTANCE: invention is meant for use in high-performance computer systems, particularly in digital signal processing systems operating in real time, in high-speed process control systems, as a means of enhancing performance in personal computers when solving problems associated with simplification of matrix form of systems of linear equations (algebraic and differential), realised as a subcircuit in an arithmetic processor or as part of a separate device (special-purpose processor). In one version, the apparatus has a pseudo-rotation unit and a normalisation unit; components of a two-dimensional vector are transmitted to the input, a first (zero) component of the resultant vector and a turning angle code are obtained at the outputs, wherein the input of the normalisation unit is connected to the output of the pseudo-rotation unit and is a six-link chain of stages, wherein the output of the previous stage is connected to the input of the next stage, each stage, along with a subtractor (adder), comprising a register, the input of the register being the input of the stage, the output of the register being connected to the first input of the subtractor (adder) and the output of the subtractor (adder) being the output of the stage.EFFECT: fewer adders required for normalisation and high performance.2 cl, 6 dwg |
