| 摘要 |
PURPOSE: A delay locked loop is provided to reduce an update cycle to correspond to delay time due to replica delay by changing the arrangement location of the replica delay. CONSTITUTION: A replica delay(221A) outputs a first delay clock by delaying a source clock in a clock path corresponding to the first delay time. A control signal generating circuit generates a control signal in response to the source clock and the first delay clock. A first variable delay line(230) delays the source clock in response to the control signal with the second delay time and outputs the delay locked clock. [Reference numerals] (210) Input buffer unit; (221A) Replica delay(D3=D1+D2); (221B) Second variable delay line; (223A) Phase comparator; (223B) Delay control unit; (230) First variable delay line; (240) Output driver |
