发明名称 |
Synchronous global controller for enhanced pipelining |
摘要 |
The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.
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申请公布号 |
US8379478(B2) |
申请公布日期 |
2013.02.19 |
申请号 |
US201213435020 |
申请日期 |
2012.03.30 |
申请人 |
BROADCOM CORPORATION;ANVAR ALI;WINOGRAD GIL I.;TERZIOGLU ESIN |
发明人 |
ANVAR ALI;WINOGRAD GIL I.;TERZIOGLU ESIN |
分类号 |
G11C8/00;G06F13/40;G11C5/06;G11C7/10;G11C7/18;G11C7/22;G11C8/10;G11C11/413;G11C11/419;G11C29/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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