发明名称 Adaptive bandwidth phase-locked loop
摘要 A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal. In addition, the size of the input capacitor is relatively small so that the circuit requires very little space.
申请公布号 US8378725(B2) 申请公布日期 2013.02.19
申请号 US201113046789 申请日期 2011.03.14
申请人 FREESCALE SEMICONDUCTOR, INC.;THAKUR KRISHNA;JAIN DEEPENDRA K.;JAIN VINOD K. 发明人 THAKUR KRISHNA;JAIN DEEPENDRA K.;JAIN VINOD K.
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
主权项
地址