发明名称 |
3T DRAM cell with added capacitance on storage node |
摘要 |
A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node.
|
申请公布号 |
US8379433(B2) |
申请公布日期 |
2013.02.19 |
申请号 |
US20100882355 |
申请日期 |
2010.09.15 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;HOUSTON THEODORE W.;KULKARNI MAKARAND R.;LAN JAMES (HSU-HSUAN) |
发明人 |
HOUSTON THEODORE W.;KULKARNI MAKARAND R.;LAN JAMES (HSU-HSUAN) |
分类号 |
G11C11/24 |
主分类号 |
G11C11/24 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|