发明名称 |
Self-test method for interface circuit |
摘要 |
An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
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申请公布号 |
US8378699(B2) |
申请公布日期 |
2013.02.19 |
申请号 |
US20090430832 |
申请日期 |
2009.04.27 |
申请人 |
RAMBUS INC.;STOTT BRET;YEUNG PHILIP;BROOKS JOHN W.;LAU BENEDICT;TRAN CHANH V.;HO EUGENE C. |
发明人 |
STOTT BRET;YEUNG PHILIP;BROOKS JOHN W.;LAU BENEDICT;TRAN CHANH V.;HO EUGENE C. |
分类号 |
G01R31/20;G01R31/26 |
主分类号 |
G01R31/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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