发明名称 |
Technique for fast power estimation using probabilistic analysis of combinational logic |
摘要 |
A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.
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申请公布号 |
US8380656(B2) |
申请公布日期 |
2013.02.19 |
申请号 |
US20090610194 |
申请日期 |
2009.10.30 |
申请人 |
ORACLE AMERICA, INC.;SUNDARESAN KRISHNAN;HUNG WEI-LUN;OH JAEWON;MAINS ROBERT E. |
发明人 |
SUNDARESAN KRISHNAN;HUNG WEI-LUN;OH JAEWON;MAINS ROBERT E. |
分类号 |
G06F15/00;G06F15/18;G06F17/50 |
主分类号 |
G06F15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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