| 摘要 |
An MOS integrated circuit including active devices and potential parasitic devices in which the threshold voltage at the active devices is relatively low, but is relatively high at the locations of the parasitic devices. One embodiment of the circuit includes a substrate and an epitaxial layer of the same polarity thereon, with the resistivity of the latter being significantly greater than that of the former. The high-resistivity epitaxial layer is present at the channel region of the active devices, but is not present at the locations of the parasitic devices. In a second embodiment of the invention, the circuit includes a substrate of high resistivity and selectively diffused regions with doping concentration significantly greater than in the substrate. The active devices are formed in the high resistivity regions and the parasitic devices are formed in the selectively diffused regions. |
