发明名称 Mapping quality of service parameters in a transaction to priority levels to allocate resources to service transaction requests.
摘要 <p>An integrated circuit (2) includes a plurality of transaction sources (6, 8, 10, 12, 14, 16, 18, 20) communicate via a ring-based interconnect (30) with shared caches (22, 24) each having an associated points of coherence/points of serialization (POC/POS)(30, 34) serving as a request servicing circuit. The request servicing circuits each have a set of processing resources (Fig 2, 36) that may be allocated to different transactions either dynamically or statically. Each transaction request from a source has an associated quality of service (QoS) value form within a range of values. The servicing circuit maps the QoS value to a priority value within a hierarchy of priority levels (Fig 5). The circuitry is configured to provide a maximum number of resources that can be concurrently allocated to service requests within each level of the priority hierarchy (Fig 3). A starvation ratio may be used to ensure that lower priority levels are also serviced.</p>
申请公布号 GB2493594(A) 申请公布日期 2013.02.13
申请号 GB20120010138 申请日期 2012.06.08
申请人 ARM LIMITED 发明人 JAMSHED JALAL;MARK DAVID WERKHEISER;BRETT STANLEY FEERO;MICHAEL ALAN FILIPPO;RAMAMOORTHY GURU PRASADH;PHANINDRA KUMAR MANNAVA
分类号 G06F13/18;G06F9/48;G06F9/50;G06F13/374 主分类号 G06F13/18
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