| 摘要 |
An input circuit includes an interface structured to output a logic signal from an alternating current signal of a pair of elongated conductors. A load is switchable to the elongated conductors. A processor outputs a control signal to switch the load to the elongated conductors asynchronously with respect to the alternating current signal for a first predetermined time, inputs the logic signal, determines if the input logic signal is active a plurality of times during the first predetermined time and responsively sets a first state of the alternating current signal, and, otherwise, sets an opposite second state of the alternating current signal, and delays for a second predetermined time, which is longer than the first predetermined time, for the opposite second state before repeating the output, and, otherwise, delays for a third predetermined time, which is longer than the second predetermined time, for the first state before repeating the output.
|
