发明名称 DES hardware throughput for short operations
摘要 A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.
申请公布号 US8374343(B2) 申请公布日期 2013.02.12
申请号 US20080106013 申请日期 2008.04.18
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;LINDEMANN MARK;PEREZ RONALD;SMITH SEAN WILLIAM 发明人 LINDEMANN MARK;PEREZ RONALD;SMITH SEAN WILLIAM
分类号 G09C1/00;H04L9/28;H04L9/06;H04L9/12 主分类号 G09C1/00
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