发明名称 |
Dual loop phase locked loop with low voltage-controlled oscillator gain |
摘要 |
A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.
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申请公布号 |
US8373460(B2) |
申请公布日期 |
2013.02.12 |
申请号 |
US201113072818 |
申请日期 |
2011.03.28 |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;SINHA ANAND K.;WADHWA SANJAY K. |
发明人 |
SINHA ANAND K.;WADHWA SANJAY K. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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