发明名称 |
Preventing fast read before write in static random access memory arrays |
摘要 |
A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.
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申请公布号 |
US8375172(B2) |
申请公布日期 |
2013.02.12 |
申请号 |
US20100761618 |
申请日期 |
2010.04.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;CHAN EDDIE K.;LEE MICHAEL J.;NIGAGLIONI RICARDO H.;TRUONG BAO G. |
发明人 |
CHAN EDDIE K.;LEE MICHAEL J.;NIGAGLIONI RICARDO H.;TRUONG BAO G. |
分类号 |
G06F12/00;G06F13/00;G06F13/28;G11C7/00;G11C11/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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