| 摘要 |
A pulse width modulator (PWM) control system for a power converter achieves a fast transient response and low steady-state jittering. The control system manages the ADC sample timing to reduce noise susceptibility, and the ADC includes a regulation bin or dead band to minimize large phase corrections and thus eliminate limit cycling. The PWM module includes a dithering circuit to accumulate fractional PWM control signals to reduce period jitter by increasing the effective resolution of the pulse width modulator.
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