发明名称 |
Digital PLL with automatic clock alignment |
摘要 |
One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal.
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申请公布号 |
US8373472(B2) |
申请公布日期 |
2013.02.12 |
申请号 |
US201113164096 |
申请日期 |
2011.06.20 |
申请人 |
INTEL MOBILE COMMUNICATIONS GMBH;THALLER EDWIN;MARSILI STEFANO;LI PUMA GIUSEPPE |
发明人 |
THALLER EDWIN;MARSILI STEFANO;LI PUMA GIUSEPPE |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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