发明名称 TEST SYSTEM FOR DATA PROCESSOR
摘要 PURPOSE:To reduce the semiconductor chip area, by utilizing the inner bus originally present in the central processor of one chip incorporating memory, and making unnecessary te exclusive bus through the connection of input and output port to this. CONSTITUTION:The program instruction in the read only memory 11 constituting the central prcessor is given to the multiplexer 13 having the control input terminal 25 through the bus 12, and this output is set in the instruction register 15 via the bus 14. Next, this instruction is added with the decoder 17 through the bus 16 where it is interpreted, and it is outputted to the output port 19 via the internal bus 18 or is fetched in the bus 18 as data through the input port 21. In testing the unit of this constitution, the input and output port 23 is connected to the bus 18 and the bus 18 is connected to the input side of the multiplexer 13 via the bus 31. Further, the output bus 16 of the register 15 is connected to the bus 18 through the bus 32 and the content of the register 15 is fed to the bus 18. Thus, the buses for exclusive use of instruction and output are made unnecessary.
申请公布号 JPS5498546(A) 申请公布日期 1979.08.03
申请号 JP19780005982 申请日期 1978.01.23
申请人 NIPPON ELECTRIC CO 发明人 NAGOYA MITSUTOSHI;IWASAKI JIYUNICHI
分类号 G06F11/22;G06F9/30;G06F11/00;G06F15/78 主分类号 G06F11/22
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