| 摘要 |
A circuit for the rapid transmission of data is presented. The circuit includes a control unit, a data storage unit, and a data processing unit. The data processing unit includes an interrupt module, a processor chipset, an access controller, a first register and a second register. The interrupt module is connected to the control unit and receives an interrupt signal from the control unit. The access controller reads data from the data storage unit according to a beginning address and an ending address included in the interrupt signal and stores the retrieved data alternately in the first register and in the second register. The processor chipset retrieves and displays data from the second register when data is in the first register and retrieves and displays data from the first register when data is in the second register.
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