LOW THRESHOLD VOLTAGE AND INVERSION OXIDE THICKNESS SCALING FOR A HIGH-K METAL GATE P-TYPE MOSFET

摘要

A structure has a semiconductor substrate (8) and an nFET and a pFET disposed upon the substrate (8). The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate (8) and a gate dielectric having an oxide layer (20) overlying the channel region and a high-k dielectric layer (30) overlying the oxide layer (20). A gate electrode overlies the gate dielectric and has a lower metal layer (40) abutting the high-k layer, a scavenging metal layer (50) abutting the lower metal layer (40), and an upper metal layer (60) abutting the scavenging metal layer (50).