发明名称 |
Clock Control of Pipelined Memory for Improved Delay Fault Testing |
摘要 |
In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.
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申请公布号 |
US2013036337(A1) |
申请公布日期 |
2013.02.07 |
申请号 |
US201113198324 |
申请日期 |
2011.08.04 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;VENKATASUBRAMANIAN RAMAKRISHNAN;KALE SUMANT;CHACHAD ABHIJEET ASHOK |
发明人 |
VENKATASUBRAMANIAN RAMAKRISHNAN;KALE SUMANT;CHACHAD ABHIJEET ASHOK |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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