发明名称 |
OVERLAY ALIGNMENT MARK AND METHOD OF DETECTING OVERLAY ALIGNMENT ERROR USING THE MARK |
摘要 |
A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.
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申请公布号 |
US2013032712(A1) |
申请公布日期 |
2013.02.07 |
申请号 |
US201113196200 |
申请日期 |
2011.08.02 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.;SHIH CHI-YUAN;HUANG I-HSIUNG;LIU HENG-HSIN |
发明人 |
SHIH CHI-YUAN;HUANG I-HSIUNG;LIU HENG-HSIN |
分类号 |
G01N23/00;H01L23/544 |
主分类号 |
G01N23/00 |
代理机构 |
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主权项 |
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地址 |
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