发明名称 LAYOUT DESIGN APPARATUS AND LAYOUT DESIGN METHOD
摘要 A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.
申请公布号 US2013036396(A1) 申请公布日期 2013.02.07
申请号 US201213534141 申请日期 2012.06.27
申请人 FUJITSU LIMITED;ARAYAMA MASASHI;WATANABE YUUKI 发明人 ARAYAMA MASASHI;WATANABE YUUKI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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