| 摘要 |
PURPOSE:To simplify a circuit constitution, by providing the hardware for such as an up-down counter and a gate circuit, and detecting the code error without taking word as to all definite quasi-tri-state codes of a digital integration value. CONSTITUTION:When a code S1 is a high level H, a code S2 is a low level L and a clock CLK changes from L to H in an up-down counter 1, then a count value of outputs Q0-Q3 is -1, and when the code S1 is L, the code S2 is H and the CLK changes from L to H, the count value of the outputs Q0-Q3 is +1. Further, when the codes S1, S2 are H and the CLK changes L to H, then the previous count value is kept as it is. The output of the counter 1 being 0 is detected at an NOR gate 4 and the output of the counter 1 being 5 is detected at an NOR gate 7 and inverters 5, 6, the output of the gates 4, 7 is applied to OR gates 2, 3 and the range of count of the counter 1 is limited between 0-5. The digital integration value of the quasi-tri-state code to be detected is assumed as 6 to detect code errors. |
