发明名称 SPEED CONVERTER
摘要 PURPOSE:To prevent missing of a picture signal to each scanning line and to improve the picture quality, by repetitively operating a storage circuit in the timing of write and readout alternately, and continuing readout when the storage circuit during readout reaches the write timing. CONSTITUTION:Storage circuits M1, M2 are provided with a write start pulse generating circuit 1, a write address generating circuit 2, a readout start pulse generating circuit 3, a readout address generating circuit 4, and a synchronizing clock generating circuit 7'. Furthr, a timing pulse generating circuit 10 and a switching circuit 11 inputting the clock of the circuit 7' are provided, write and readout timing pulses (w), (r) are generated from the circuit 10, and the circuit 11 instructs the write and readout of the circuits M1, M2 in response to the pulses (w) and (r). The circuits M1, M2 are alternately operated in the timing of write and readout repetitively, and when the circuit M1 or M2 in the readout reaches the write timing, the readout is continued to improve the picture quality.
申请公布号 JPS5869166(A) 申请公布日期 1983.04.25
申请号 JP19810169261 申请日期 1981.10.21
申请人 NIPPON DENKI KK 发明人 OCHI HISAKATSU
分类号 H04N1/21;H04N1/04 主分类号 H04N1/21
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