发明名称 TIME DIVISION MULTIPLEX TRANSMISSION SYSTEM
摘要 PURPOSE:To reduce the response time of a CPU by providing an interruption selecting circuit selecting whether or not the transmission of an interruption request signal is inhibited to a terminal device, and calling the terminal device inhibited for the transmission of the interruption request signal from the CPU by individual polling to allow the terminal device to return a signal. CONSTITUTION:The terminal device 2 has a supervising input change detecting circuit 2a detecting a change in a supervised input WS and when the circuit 2a detects the change in the supervised input WS, the circuit 2a outputs an interruption signal IS to a terminal signal processing circuit 2b. This line 2b transmits the interruption request signal to the CPU via a signal line 3 during the reception of the interruption request standby signal VS of the transmission signal. An interruption selecting circuit 4 selects whether the transmission of a signal IRQ is inhibited or not, and the terminal device 2 is operated in the high speed mode outputting the signal IRQ at the change in the supervised input when an interruption selection signal E/D is logical 1 and operated in the low speed response mode not outputting the signal IRQ when the signal E/D is logical 0.
申请公布号 JPS59231947(A) 申请公布日期 1984.12.26
申请号 JP19830106895 申请日期 1983.06.15
申请人 MATSUSHITA DENKO KK 发明人 AKIBA OSAMU;SUZUKI YOSHIHARU;TERADA MOTOHARU;SAEKI TAKASHI
分类号 H04L5/22;G06F13/24;(IPC1-7):H04L11/00;H04J3/00 主分类号 H04L5/22
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