| 摘要 |
PURPOSE:To speed up a processor even when address conflict is occurred by providing a means that discriminates an instruction using only data not stored in a main memory as data necessary for calculation. CONSTITUTION:When an AR instruction is stored in an instruction register IR 13, the R1, R2 parts are sent to a general-purpose register 24, and the first operand and the second operand are outputted from R1, X2 ports and sent to a D stage preceding arithmetic unit PAD 32. A selector SEL 36 selects the output of the PAD 32, that is, the result of D stage precedent operation of the AR instruction instead of output of the B2 port of the GR 24, and is inputted to the B2 port of an address adder AA 21. Thus, the value of a base register necessary for an L instruction can be obtained from the PAD 32 without waiting until the result of operation of the AR instruction is obtained in an arithmetic unit FU 3, and address calculation can be made immediately.
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