Dual domino CMOS logic circuit, including complementary vectorization and integration.

摘要

At each stage of a domino CMOS logic circuit, the output signal Y1 and its inversion @1 are separately generated in mutually complementary first and second logic networks in each such stage. These outputs are then used as inputs for succeeding domino logic stages. In this way, all inputs are guaranteed to be low at the end of the precharging phase as is desired for all inputs to all domino logic.