发明名称 |
Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory |
摘要 |
A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
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申请公布号 |
US8370557(B2) |
申请公布日期 |
2013.02.05 |
申请号 |
US20080340022 |
申请日期 |
2008.12.19 |
申请人 |
INTEL CORPORATION;DAMA JONATHAN;LINES ANDREW |
发明人 |
DAMA JONATHAN;LINES ANDREW |
分类号 |
G06F13/00;G06F12/00;G11C11/413 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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