| 摘要 |
A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.
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