| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a block matching processing circuit for which power consumption is substantially reduced. <P>SOLUTION: The block matching processing circuit comprises: a computing element for obtaining a difference absolute value of two input signals; an adder circuit for successively and hierarchically adding all computation results of the computing element; first and second accumulators for accumulating output results of the adder circuit; a 1-to-2 distributor and a 1-to-4 distributor for respectively dividing accumulation results time-sequentially outputted from the first and second accumulators; a first register for storing an output result of the 1-to-2 distributor; an adder for adding values of the first register; a second register for storing an output result of the adder; a third register for storing an output result of the 1-to-4 distributor; an adder for adding values of the third register; a fourth register for storing an output result of the adder; an adder for adding values of the fourth register; and a fifth register for storing an output result of the adder. The first-fifth registers output a difference absolute value sum. <P>COPYRIGHT: (C)2013,JPO&INPIT |
