发明名称 FUSE BUS FOR PLATING FEATURE ON SEMICONDUCTOR DIE
摘要 <P>PROBLEM TO BE SOLVED: To provide a method of electroplating a feature structure such as an interconnection part or a bond pad on a semiconductor die. <P>SOLUTION: The method comprises the steps of: forming a plurality of fuses (208) over a semiconductor substrate; and forming a plurality of interconnection layers (400-408) over the semiconductor substrate and a plurality of interconnection pads (502) on upper surfaces of the plurality of interconnection layers. A seal ring (202) is formed around an active circuit formed in and on the semiconductor substrate (302), the plurality of interconnection pads (502), and the plurality of fuses (208, 320). Each fuse (208, 320) is electrically connected to a corresponding interconnection pad (502) and the seal ring (202). When each fuse (208) is in a conductive state, the fuse electrically connects the corresponding interconnection pad (502) to the seal ring (202). <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013026624(A) 申请公布日期 2013.02.04
申请号 JP20120159145 申请日期 2012.07.18
申请人 FREESCALE SEMICONDUCTOR INC 发明人 GEORGE R LEAL;KEVIN J HESS;TRET S YULIN
分类号 H01L21/3205;H01L21/768;H01L21/82;H01L23/522 主分类号 H01L21/3205
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