发明名称 ARITHMETIC CONTROL UNIT, ARITHMETIC CONTROL METHOD AND PROGRAM AND PARALLEL PROCESSOR
摘要 <P>PROBLEM TO BE SOLVED: To reduce the labor of a developer of a user code, and to increase the portability of the user code about data movement between a plurality of memories accompanied by a parallel arithmetic operation with respect to a parallel processor. <P>SOLUTION: An attribute group storage part 132 is configured to acquire and store an attribute group set for each data block. A scenario determination part 134 is configured to determine the transfer system of each data block between a memory of the lowermost-rank hierarchy and a memory of another hierarchy on the basis of those attribute groups and a configuration parameter showing the configurations of an arithmetic unit 140 as a parallel processor, and to perform the transfer of each data block and the control of a parallel arithmetic operation corresponding to the transfer in accordance with the determined transfer system. The attribute group, which is necessary for determining the transfer system, includes one or more attributes which do not depend on the configurations of the parallel processor. The attribute group of a write block is set assuming that the write block already exists in the memory of the other hierarchy, and that the write block is transferred to the memory of the lowermost-rank hierarchy. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013025547(A) 申请公布日期 2013.02.04
申请号 JP20110159396 申请日期 2011.07.20
申请人 RENESAS ELECTRONICS CORP 发明人 KYO SHIYOURIN
分类号 G06F15/80;G06F12/08 主分类号 G06F15/80
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