发明名称 Method for producing electrical connection in semiconductor substrate of integrated device in three-dimensional integrated structure, involves forming layer on part of carrier located between pillars to produce electrical connection
摘要 <p>The method involves realizing a cavity in a carrier from a surface, and filling the cavity with electrically conductive material to obtain an electrically conductive pillar. The carrier is engraved from another surface opposite to the former surface to reach a bottom of the conductive pillar and form a silicon pillar. An electrically conductive layer (CC) projecting from the silicon pillar is formed on the bottom of the conductive pillar and on a part of the carrier located between the pillars to produce an electrical connection. Independent claims are also included for the following: (1) an integrated device (2) a three-dimensional (3D) integrated structure.</p>
申请公布号 FR2978609(A1) 申请公布日期 2013.02.01
申请号 FR20110056817 申请日期 2011.07.26
申请人 STMICROELECTRONICS (CROLLES 2) SAS 发明人 BOUCHOUCHA MOHAMED;CHAPELON LAURENT-LUC
分类号 H01L21/60;H01L23/12 主分类号 H01L21/60
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