| 摘要 |
An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer.
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