| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delayed clock signal generation circuit that cancels delay times of multiplexers for switching a delay path. <P>SOLUTION: The delayed clock signal generation circuit includes: a delay circuit 10 comprising N series-connected unit delay stages 13 and receiving a clock signal CLK1 at the unit delay stage 13 of the first stage; a correction circuit 20 comprising N series-connected multiplexers 21 having the same delay time as multiplexers 12 of the unit delay stages 13 and receiving the clock signal CLK1 at the multiplexer 21 of the first stage; a DLL control circuit 30 for controlling a delay of each unit delay stage 13 of the delay circuit 10 such that a phase difference of an output clock signal CLKA of the delay circuit 10 from an output clock signal CLKB of the correction circuit 20 becomes equal to one period of the clock signal CLK1; and adjustment circuits 60A, 60B each comprising N series-connected multiplexers 61 having the same delay time as the N series-connected multiplexers 12. <P>COPYRIGHT: (C)2013,JPO&INPIT |
